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Unit:

Microelectronic Design

Unit 3: Integrated Circuit Packaging


Unit Overview

This Unit covers the topic of Integrated Circuit Packaging


Unit Contents

NOTE: If you require further detailed information on packaging you can refer to

Microelectronics Packaging Handbook, 
Edited by Rao R Tummala, 
Eugene J Rymaszewski. Van Nostrand Reinhold. 
ISBN: 0-412-08561-5
Vols 1,2,3.
Also available on CD-ROM.

However this is a specialised book which is not held in many libraries. The library at BI has one copy.


3.1 Introduction

  • Packaging of ICs is the ability to establish interconnections between the chip and package and package to PCB, etc. and maintain a suitable operating environment for the IC to function effectively and efficiently.
  • Key aspects are topological, electrical, thermal and reliability.
  • IC package has four major functions:
  • Power distribution, involving EM, structural and material aspects.
  • Signal distribution, involving topological and EM aspects.
  • Heat dissipation (cooling), involving structural and material considerations.
  • Circuit protection, (mechanical, chemical, EM) of components and interconnections.

Packaging process must be cheap, mechanically robustand reliable.

 

Figure 3.1 Four major functions of the package

Figure 1. Four major functions of the package


 

Figure 3.2 Commercial IC

Figure 3.2 Commercial IC



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3.2 Design Considerations

Successful package will satisfy all application requirements at an acceptable design, manufacturing and operating cost.

Improving technology increases the demands on the number and density of package pins and interconnections demanding reduced physical dimensions requiring the use of improved techniques.

Need to improve quality and reliability of the packaging process important.

Number of connections (pin-out) a major cost factor and strongly dependent on IC function, eg. memories require few connection pins but random logic requires many more.

The number of terminals (pins) required and the number of circuits are related by Rent's Rule which states that

N = KMp  where N is the number of input-output terminals required, K is the average number of terminals used for an individual logic circuit, M is the total number of circuits and p is a constant Rent is constant (0 <= p <= 1).  Typically p is 0.12 for static memory, 0.45 for microprocessors and 0.63 for high performance computer chips.

Graph 1 shows pin-out for memory and random logic ICs showing memories requiring relatively few pins whereas random logic requires many and approximately follows Rent’s Rule.  Graph 1 - Graph of number of pins (terminals) versus circuit complexity for various microelectronic functions

Graph 1 - Graph of number of pins (terminals) versus circuit complexity for various microelectronic functions

Graph 1 - Graph of number of pins (terminals) versus circuit complexity for various microelectronic functions

 

Increasing pin-out requires the package to squeeze more pins into the same or less space whilst still maintaining requirements of mechanical fragility, electrical performance and thermal specification.

 

3.2.1 Electrical Considerations

  • Basic package electrical parasitics of resistance, inductance and capacitance present in all IC packages and can cause signal delays, signal distortion and noise.
  • Self-capacitances in particular cause signal delays.
  • Non-zero source resistances also increase signal delays.
  • New more complex packages have reduced self-capacitances (by using improved geometry and lower dielectric constant materials) and reduced source resistances.
  • Package resistance causes voltage drops and increases signal delays.
  • Signal reflections are particularly troublesome causing faulty circuit operation in some cases.
  • Noise generated by switching current from one chip driver can affect other drivers through inductances.
  • Reduce noise by reducing inductances, restricting the total switched current, or using decoupling capacitors.
  • Power distribution across a chip must be accurately controlled (<10% variation maximum) so package power lines must be designed to ensure this happens even in the event of circuit switching activity.

 

3.2.2 Thermal Considerations

  • More complex chips make more demands on efficient heat removal from the chips.
  • Silicon chips limited to approximately 100ºC for normal operation which limits power densities on chip to a maximum of 10watts/cm2 in current IC packages.
  • Imposes a limit average on power dissipation per individual circuit on chip of approximately 1µW/circuit for a 10 million transistor chip of area 1cm × 1 cm.
  • Important to reduce power dissipation/circuit and improve package thermal design in order to produce larger, more complex ICs in the future.
  • Differential thermal expansion of package parts gives rise to mechanical stresses and reliability risks.


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3.3 IC Packaging Technologies

  • Total package technologies in electronic products are very diverse and include ICs, PCBs, flexible circuit carriers and Multi-Chip Modules (MCMs) as shown in Table 1.

 

 

Table 1 - Typical packaging technologies

  Chip  connection  1st level package 1st to 2nd  level   connection 2nd level package 2nd to 3rd  level   connection  3rd level package Chip   cooling Max   chips/   system
  Consumer electronics              
  WB  PSCM  SMT/PTH  Card  - <10 
  WB/TAB  PSCM  SMT/PTH  Card   
  WB  PSCM  SMT/PTH  Card/flex   
  Low-end systems              
  WB  PSCM  SMT/PTH  Card  Connection  Board  10s 
  WB  PSCM  SMT/PTH  Card  Connection  Board   
  WB  PSCM  SMT/PTH  Card   
  WB  PSCM  SMT/PTH  Card   
  WB  PSCM  SMT/PTH  Card/flex   
  Intermediate systems              
  WB  C-SCM  PTH  Card  Connection  Board  Air  100s 
  WB  C-PGA  SMT  Card  Connection  Board  Air (w/fin)   
  WB  C-PGA  PTH  Card  Connection  Board  Air   
  C4  C-TCM  PTH  Board  Connection  Cable  Air   
  Large systems              
  WB  C-L-CC SMT  P-G board  Connection  Cable  Water  1,000s
  WB  C0FP C-MCM  PTH  P-G board  Cable  P-G board  Air   
  C4  C-TCM  PTH  FR-4 board  Connection  Cable  Water   
  TAB  FTC  SMT  LCM  PTH  P-G board  Water   
  Supercomputers              
  WB  C-FP  SMT  Card  Connection  Cable  FC-78  >10,000 
  TAB  C-LCC  SMT  Board  Connection  Cable  LN2  
  TAB  FTC  SMT  LCM  PTH  P-G board  Water   



 

C - FP: Ceramic flat pack LCM: Liquid cooled module
  Ceramic leaded chip carrier PC: Personal Computer
C - MCM: Ceramic multichip module PGA: Pin grid array
Conn: Connector P-G Board:  Polyimide-glass board
C - PGA: Ceramic pin grid array PSCM: Plastic single chip module
C - SCM: Ceramic single chip module PTH: Pin-through-hole
C - TCM: Ceramic Thermal conduction module SMT: Surfacemount technology
FC - 78: Fluorocarbon liquid TAB: Tape automated bonding
FR - 4 Board:  Epoxy-glass board TCM: Thermal conduction module
FTC: Flip TAB carrier WB: Wirebond
LCC:  Leaded chip carrier    

 

  • A wide range of different materials used in packages as shown in Table 2.

 

Table 2 - Packaging technologies and processes

Technology   function  Technology   options  Typical   materials  Typical   process  Typical   process   temperature  oC
Connection to chip  Wirebond  Gold, aluminium  Wirebond  225 
  Solder bond (C4)  Pb-Sn  Reflow  360 
  TAB  Copper, gold,   aluminium, polyimide  Thermocompression  550 
1st level package  Ceramic  Al2O3, SiC, BeO  Sintering  1,500-2,000 
  Plastic  Epoxy  Moulding  200 
  TAB  Cu on Kapton® Adhesive bond  200 
1st to 2nd level connection  Surface mount solder  Pb-Sn  Reflow  220 
  Pin-in-hole solder  Kovar, Pb/Sn  Reflow  220 
  Pin braze  Kovar, Au/Sn  Braze  400 
2nd level package Card Epoxy glass Cure 200
  Metal carrier  Glass on steel, invar  Fuse  1,000 
  Flex  Cu on Kapton® Adhesive bond 200 
  Injection moulding card  Resin  Moulding  200 
3rd level package  Board  Epoxy glass  Cure  175 
    Polyimide, glass  Cure  200 
2nd to 3rd level connection  Connector  Polymer, BeCu  Cure  200 
  Cable  Polymer, copper  Cure  200 
Note: Kapton is a trademark of Dupont Company       
  • Packaging hierarchy imposes thermal hierarchy considerations on the assembly of the total system.

 

3.3.1 Chip Package Connection

  • Connections between the chip and package commonly performed by one of the following three technologies:
    • Wirebond using thin gold or aluminium wire.
    • Solder bond or Controlled Collapse Chip Connection (C4), also called flip-chip.
    • Tape Automated Bonding (TAB).
  • Wirebond most common, cheapest, lowest temperature but limited in the number of connections that can be made (<500) and also high lead inductance limiting electrical performance.
  • C4 capable of many more connections up to 20k and low lead inductance but more complex technology and higher temperature.
  • TAB gives higher number of connections than wirebond though not as high as C4, better electrical performance, high yield and lower assembly costs but highest temperature and more complex technology.

 

3.3.2 Chip Packages

  • Chip packages are made of metal, ceramics and are either hermetically sealed or encapsulated in plastic.
  • The most common types are:
     

 

Dual-In-Line (DIP) and variants 

Pin Grid Array (PGA)

Intended for the older ‘through the board’ style
Leadless Chip Carrier (LLCC) 

Small Outline Package (SOP) 

Leaded Chip Carrier (PLCC) 

Quad Flat Pack (QFP) 

Tape Automated Bonding (TAB) 

Chip Scale Packages

Intended for the cheaper surface mount technology

 

  • Their main characteristics are given in Table 3:
     

 

Table 3 - First level single chip packages and their characteristics

Package Package materials Number of   interconnections Future I/O spacing   (mm)
Dual-in-line Alumina ceramic, plastic  64   64  
2.54
2.54
Shrink DIP  Plastic  64   
1.77
Skinny DIP  Plastic  64   
2.54 
Single-in-line (SIP) Plastic  21  
2.54 
Leadless chip carrier (LLCC)  Ceramic  132   
1.27 
    300 
400
0.63 
  Plastic 180
 
1.00
Small outline package  (SOP)  Plastic  40 
 
1.27 
Leaded chip carrier (LCC)  Plastic  84 
 
1.27 
    144
 
0.63
Quad Flat pack (QFP)  Plastic  130 
 
1.00 
    160 
500
0.65 
  Ceramic  180 
 
0.40 
    200 
 
0.63 
Very small peripheric array    300 
600
.0.40 
     
500
0.40
Pin-grid array (PGA)  Alumina (single chip)  312 
 
2.54 
     
>1000
1.27
  Ceramic (multichip)  2177 
>5000
2.54 
  Plastic  240 
 
2.54 
     
>500
2.54
Tap automated bonding (TAB)  Plastic  300 
>1000
0.50
0.25
Ball grid array  Plastic 
Ceramic
300   604
>500 
>1000
0.50
0.40
Chip Scale packages Thin film ceramic 300-1000 
300-1000
>1000 
>1000
0.5
0.5
SLIM Thin film -
>5000
0.25

 

  • IC packages have to:
    • Provide the required number of pins for power and signals.
    • Ensure thermal expansion compatibility with the chip.
    • Have a thermal path for heat removal from the chip.
    • Keep signal delays and noise to a minimum.
  • Low dielectric constant materials used where possible to reduce signal delays.
  • High thermal conductivity materials used to give good thermal properties.
  • Area occupied by packages on PCB often an important concern.
  • Other aspects sometimes important are burn-in ability, test, solder bond or socket to PCB and field upgradeability.
  • Costs always important - Graph 3 gives a plot of cost per lead ratio versus number of pins for the common packages.

 
 

Graph 3 - Cost per lead ratio versus number of I/O pins

Graph 3 - Cost per lead ratio versus number of I/O pins

 


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3.4 Package Cooling Considerations

  • Despite reductions in power dissipation/individual circuit due to technology improvements, current chips contain more individual circuits/chip and so total power dissipation/chip is increasing.
  • Graph 4 shows a plot of typical power dissipation per chip between 1970-1990 showing at least a tenfold increase over that period.
  • Most systems use forced-air cooling of modules for package cooling.

 

Graph 4 - Power per chip versus year of first use

Graph 4 - Power per chip versus year of first use
  • High performance systems additionally use heat sinks mounted onto packages using various technologies.
  • In extreme cases packages are further cooled by immersion in inert liquids, such as fluorocarbons.

 


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3.5 Package Sealing and Encapsulation

  • Intended to protect the chip and package metallisation from corroding environments and from mechanical damage due to handling.
  • Moisture is one of the major sources of corrosion.
  • Plastic materials, such as silicones and epoxies, developed with low water diffusion properties are used extensively for IC encapsulation.
  • For high reliability devices hermetic sealing used based on welding or brazing of ceramic/metal packages. More expensive and time-consuming than plastic encapsulation.

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 3.6 WWW Research
Use the following to search the www:
  • IC packaging, cooling, encapsulation, wire bonding, flip-chip, TAB, pin-out, signal delays, dual-in-line package.
  • Sematech at http://www.sematech.org

 

 


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 3.7 Self Assessment Questions

Question 1

Using Rent's Rule, evaluate for a high performance random logic application the number of I/O terminals required for:

i) a 10,000 gate chip
ii) a 1,000,000 gate chip

Question 2

i) What are the reasons for signal degradation in an IC package? 
ii) How can they be minimised? 

Question 3

i) What is the Tape Automated Bonding (TAB) technique for IC packaging? 
ii) In what applications it is likely to be used? 

show solution
Text & images © 2003 Bolton Institute.
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